To provide a metal gate between a source region and a drain region on a semiconductor substrate, it is conventional practice to deposit a layer of metal on a surface portion of the substrate over a region (called the gate region) between the source region and the drain region. It is generally advantageous for the boundaries of the metal gate to be aligned as precisely as possible with the boundaries of the source and drain regions of the substrate in order to minimize parasitic capacitances. A masking technique is normally used to define the boundaries of the metal gate with respect to the boundaries of the source and drain regions of the substrate.
Conventionally, in forming a metal gate on a surface portion of a semiconductor substrate, a mask is placed over the surface of the substrate. The mask has a pattern of dark fields and apertures, which are arranged according to the design of the particular integrated circuit being produced on the semiconductor device. The mask is positioned so that dark fields are aligned with the source and drain regions, and so that an aperture is aligned with the gate region. The metal that is to form the gate is deposited through the aperture directly onto the surface portion of the substrate over the gate region.
In the prior art, it was generally difficult to achieve precise alignment of the boundaries of a metal gate with the boundaries of closely spaced source and drain regions on a semiconductor substrate, particularly in fabricating JFET and MOS devices for which the spacing between adjacent source and drain regions is typically on the order of 1.2 microns. Ordinarily, the precision with which the boundaries or a metal gate could be aligned with the boundaries of source and drain regions on a semiconductor substrate decreased with decreasing separation between the source and drain regions. Furthermore, uniformity in the thickness and density of the gate metal also generally decreased with decreasing separation between the source and drain regions.
In the prior art, there has been a widely acknowledged need for a technique that would enable self-aligned metal gates to be formed on semiconductor devices, particularly on very high speed integrated circuits (VHSIC) and on devices requiring very large scale integration (VLSI).